Solid State Science and Technology, Vol. 15, No 2 (2007) 190-196

ISSN 0128-7389

GATE DEPLETION ANALYSIS OF PMOSFETS WITH POLYSILICON GATE

Norhayati Soin and Desmond Soo Chin Yoong

Electrical Department, Faculty of Engineering, University of Malaya

 

ABSTRACT

This paper presents the study of the polysilicon gate depletion effect (PDE) on the threshold voltage and capacitance of PMOSFETs devices. Simulation analysis over wide range of oxide thickness, gate length width and gate doping were also performed. Simulation results proved that the polysilicon gate depletion effect caused the performance degradation in MOSFET devices due to the reduction of the total gate capacitance as the potential drop of the gate increased. The PDE effect of PMOSFETs with silicon nitride (Si3N4) as dielectric material has been proved to have better performance than the PMOSFETs with silicon dioxide (SiO2) dielectric. It has been found that the polysilicon gate is not compatible to High-K dielectric material.

http://journal.masshp.net/wp-content/uploads/Journal/2007/Jilid%202/Norhayati%20Soin%20190-196.pdf

 

REFERENCES

[1]. URL:http://www.semiconductorglossary.com

[2]. Wong, C.Y., Sun, J.Y.C., Taur, Y., Oh, C.S., Angelucci, R. and Bavari B.(1988). “Doping of n+ and p+ Polysilicon in a Dual-Gate CMOS process.“IEDM Tech.Dig.” 238-241.

[3]. Chen, K., Chan, M., Hu C., Ma, Z.J., Rabye, J.(1995). Polysilicon depletion effect on IC performance.

[4]. Schuegraf, K. F., King, C. C. and Hu, C. (1993). Int.Symp. VLSI TSA.86.

[5]. Ashawant G., Peng F., Miryeong S., Ming-Ren L., Don W., Kai Chen, and Chenming H. (1997).Accurate Determination of Ultrathin Gate Oxide Thickness and Effective Polysilicon Doping of CMOS Devices. IEEE Electron Device Letters. Vol.18 (12).

[6]. Donald Naeman. (1997). Semiconductor Physics & and Devices, BasicPrinsiple.2nd Edition.MGGraw Hill,International Edition.

[7]. Pierret, R.F. (1996). Semiconductor Device Fundamentals. Addison Wesley Publishing Co.,Reading MA.

[8]. Rios, R., Arora, N. D., and Huang, C.L., “An analytic polysilicon depletion effect model for MOSFETs,” IEEE Electron Device Lett., vol. 15,129–131, Apr. 1994.

[9]. Chang, H. C., Rajesh, K.(2002), Dopant Profile and Gate Geometric Effects on Polysilicon Gate Depletion in Scaled MOS.IEEE Transactions on Electron Devices.vol.49(7).

[10]. Hsueh, K. K., Sanchez, J. J., Demassa, T. A. and Akers, L. A. (1988). Inversenarrow-width effects and small-geometry MOSFET threshold model. IEEE Trans. Electron Devices. Vol. 35.325–338.